1. Field of the Invention
This invention relates to a method for forming deposited film and a method for forming a semiconductor device. Particularly, it pertains to a method for forming an Mo deposited film preferably applied to wiring of a semiconductor circuit device, or the like and a semiconductor device by use of the selective deposition Mo film.
2. Related Background Art
In the prior art, in electronic devices or integrated circuits by use of semiconductors, aluminum (Al) or Al-Si or the like have been primarily used for electrodes and wiring. Al is inexpensive and has a high electro-conductivity, and dense oxidized film can be formed on the surface. Accordingly, it has many advantages that the inner portion can be protected to be stabilized and adhesion to Si is good.
However, on the other hand, with higher integration, the self-align technique in which mask matching between the gate electrode and the diffusion layer, or the like is unnecessary is indispensable. Metal having low melting point such as Al cannot be used. In the MOS LSI of the prior art, as the gate electrode wiring capable of self-align, a polycrystalline Si doped with an impurity at high concentration has been widely employed. Whereas, with the progress of further higher integration, there ensues the problem that electrical resistance of fine polycrystalline Si wiring or the like becomes higher. This is vital to high speed actuation of the device. Accordingly, it has been required to have a high melting metal which is lower in volume resistivity than polycrystalline Si and yet is capable of self-align. Also, basically, even when Al can be employed, Si and the Al wiring react with each other during heat treatment at the contact electrode portion with the Si layer, whereby wire breaking or increased resistance of wiring are caused to occur. For this reason, a metal having higher melting point and lower electrical resistance has been employed as the electrode wiring material, and as the barrier metal which prevents the reaction between Si and Al at the contact portion. Particularly, Mo is attracting attention for its sufficiently high melting point (2620.degree. C.) and low electrical resistance (4.9 .mu..OMEGA..cm).
Deposition methods according to the electron beam deposition and the sputtering method have been employed to Mo film used in Mo electrodes wiring or the like of the prior art. With finer dimensional formation by increased integration degree, the surface of LSI or the like is subject to excessive unevenness due to oxidation, diffusion, thin film deposition, and etching or the like. For example, electrodes or wiring metal must be deposited on the surface with a stepped difference, or deposited in a via-hole which is fine in diameter and deep. In 4 Mbit or 16 Mbit DRAM (dynamic RAM) or the like the aspect ratio (via hole depth/via hole diameter) of via-hole in which a wiring metal is to be deposited is 1.0 or more, and the via-hole diameter itself also becomes 1 .mu.m or less. Therefore, even for a via-hole with large aspect ratio, the technique which can deposit a wiring metal is required.
Particularly, for performing sure connection to the device under insulating film such as SiO.sub.2 or the like rather than film formation, a metal is required to be deposited so as to embed only the via-hole of the device. In such case, a method of depositing a wiring metal only on Si or metal surface and not depositing it on an insulating film such as SiO.sub.2 is required.
It is difficult to achieve such a selective deposition and growth by the electronic beam deposition and sputter process used in the past. The sputter process is a physical deposition method performed by scattering the particles sputtered in vacuum. Therefore, the film thickness becomes very thin at the step portion and insulating film side wall, and the breaking of a wire may be caused in an extreme case. Further, unevenness of a film thickness and the breaking of a wire cause remarkable degradation of a reliability of LSI.
On the other hand, there has been developed the bias sputtering method in which a bias is applied on a substrate and deposition is performed so as to embed Al, Al alloy or Mo silicide only in the via-hole by utilizing the sputter etching action and the deposition action on the substrate surface. However, since the bias voltage of some 100 V or higher is applied on the substrate, deleterious influence occurs because of charged particle damaging such as change in threshold of MOS-FET or the like. Also, because of presence of both etching action and deposition action, there is the problem that the deposition speed cannot be essentially improved.
In order to solve the problems as described above, various types of CVD (Chemical Vapor Deposition) methods have been proposed. In these methods, chemical reaction of the starting gas in some form is utilized. In plasma CVD or optical CVD, decomposition of the starting gas occurs in gas phase, and the reaction species formed there further react on the substrate to give rise to film formation. In these CVD methods, surface coverage on unevenness on the substrate surface is good since the reaction occurs in a gaseous phase. However, carbon atoms contained in the starting gas molecule are incorporated into the film. Also, particularly in plasma CVD, the problem remained that there was damage by charged particles (so called plasma damage) as in the case of the sputtering method.
The thermal CVD method, in which the film grows through the surface reaction primarily on the substrate surface, is good in surface coverage on unevenness such as stepped portion of the surface. Also, it can be expected that deposition within via-hole will readily occur. Further, wire breaking at the stepped portion can be avoided.
For this reason, various studies have been made about the thermal CVD method as the method for forming Mo film. For example, there are hydrogen reduction method of MoCl.sub.5 and Si reduction method of MoF.sub.6 according to normal pressure CVD or reduced pressure CVD as introduced in Chapter 4 of Handotai Kenkyu (Semiconductor Research) Vol. 20 (Kogyo Chosakai, 1983). However, in the hydrogen reduction method of MoCl.sub.5, a plurality of molybdenum halide such as MoCl.sub.3 and others other than Mo may sometimes form at the portions other than the substrate surface heated within the film forming device. Therefore, it is difficult to control film formation. Also, although film formation may be possible, no selective deposition was observed.
On the other hand, for example, in EP 147913 (A3) Publication or U.S. Pat. No. 3,785,862, there is shown the method of forming Mo film by use of MoF.sub.6 gas, hydrogen gas and an inert gas.
Whereas, in the Si reduction method of MoF.sub.6, MoF.sub.6 reacts in the presence of Si to precipitate Mo, whereby Si is etched. Therefore, there is a fear that the electronic circuit on Si wafer may be damaged. Also, SiO.sub.2 is etched. However, for this reason, in the Si reduction method of MoF.sub.6, deposition occurs primarily on Si substrate, and Mo film deposition dose not occur on SiO.sub.2 at all, but it is clearly stated in U.S. Pat. No. 3,785,862 that Mo film is also deposited on SiO.sub.2. This suggests that selective deposition of Mo is not so complete. In addition, as described above, both Si and SiO.sub.2 are subjected to etching, and under such state there is a fear that problems may be involved practically concerning surface flatness and mixing of impurity, or the like As another method, there is an example of normal pressure CVD method of Mo(CO).sub.6 as described in Thin Solid Films, Vol. 63 (1979), p. 169. In this method, Mo film can be deposited on the substrate by use of normal pressure CVD with Ar as the carrier gas. However, in this method, a considerably large amount of oxygen and carbon in Mo film as impurities may be incorporated and for this reason, there is a fear that electrical resistance of the deposited film may be increased. Also, according to this method, selective deposition can be done with difficulty.
As described above, the deposition method of Mo film of the prior art had many problems to be improved, such that coverage of the stepped difference of the LSI surface was poor, that the Si surface of LSI was unnecessarily etched, that damage was given to SiO.sub.2, that deposition reaction could be controlled with difficulty, or that a large amount of impurities were mixed into Mo film.